1. Field of the Invention
The present invention relates to a semiconductor memory device and specifically, to a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device.
2. Discussion of Related Art
In general, data input and output operations of synchronous semiconductor memory devices are carried out in sync with an internal clock signal generated on basis of an external clock signal. Such synchronous semiconductor memory devices include single data rate (SDR) synchronous dynamic random access memory (SDRAM), double data rate (DDR) synchronous DRAM, and DDR2 SDRAM. Among them, the DDR2 SDRAM generally uses a 4-bit pre-fetch scheme. The 4-bit pre-fetch scheme is a data processing way reading 4-bit data out of memory cells in parallel in response to a single read command and then outputting the read 4-bit data through the same data input/output pin for two clock cycles. Such a DDR2 SDRAM is generally configured as shown in FIG. 1. FIG. 1 is a schematic block diagram of a multi-bit pre-fetch type semiconductor memory device including a conventional pipe latch circuit. Referring to FIG. 1, the semiconductor memory device 10 includes a controller 11, an address input circuit 12, a bank controller 13, an internal core circuit 14, an input/output gating circuit 15, a pipe latch circuit 16, an output driver 17, an input circuit 18, and an input receiver 19. The pipe latch circuit 16 receives data bits D0˜D3 supplied from the input/output gating circuit 15 through a global input/output line GIO and outputs the data bits D0˜D3 in the order of data by a sequential or interleaving mode in response to control signals PIN, SOSEZ0, SOSEZ1_RD, SOSEZ1_FD, RPOUT, and FPOUT. From FIG. 1, operations of internal blocks of the semiconductor memory device 10, except the pipe latch circuit 16, may be easily understood by those skilled in this art, so it will not be described in detail.
FIG. 2 is a detailed block diagram of the pipe latch circuit shown in FIG. 1. Referring to FIG. 2, the pipe latch circuit 10 includes a first latch circuit 20, a first multiplexing circuit 30, a second multiplexing circuit 40, a second latch circuit 50. The first latch circuit 20 includes latches 21˜24 simultaneously latching the data bits D0˜D3, which are pre-fetched from the global input/output line GIO, in response to the control signal PIN. The multiplexing circuit 30 includes multiplexers 31˜34. The multiplexers 31 and 32 select the data bits D0 and D1 independently, which are supplied from the latches 21 and 22, in response to the control signal SOSEZ1, and output the selected data bits as second data bits PRE_FD1 and PRE_FD2 respectively. The multiplexers 33 and 34 select the data bits D2 and D3 independently, which are supplied from the latches 23 and 24, in response to the control signal SOSEZ0, and output the selected data bits as second data bits PRE_FD1 and PRE_FD2 respectively. The multiplexing circuit 40 includes multiplexers 41˜42. The multiplexer 41 selects the first selected bits PRE_RD1 and PRE_RD2 in response to the control signal SOSEZ1_RD, and outputs the selected data bit. The multiplexer 42 selects the second selected bits PRE_FD1 and PRE_FD2 in response to the control signal SOSEZ1_FD, and outputs the selected data bit. The second latch circuit 50 includes latches 51 and 52. The latch 51 holds (or latches) an output signal of the multiplexer 41 in response to the control signal RPOUT, and outputs the latched signal as an output data bit RDOB. And, the latch 52 holds (or latches) an output signal of the multiplexer 42 in response to the control signal FPOUT, and outputs the latched signal as an output data bit FDOB. Here, the control signals SOSEZ0, SOSEZ1_RD, and SOSEZ1_FD are enabled in response to generation of the read command. As a result, an order of the data bits D0˜D3 output from the pipe latch circuit 16 is arranged by the control signals SOSEZ0, SOSEZ1_RD, and SOSEZ1_FD. Meanwhile, the conventional pipe latch circuit 16 aforementioned includes six multiplexers to arrange the data bits D0˜D3 in a predetermined output order. Since the pipe latch circuit is constructed with the feature that one input/output pin is connected to three or four output terminals, the pipe latch circuit more occupies the circuit area as the number of input/output pins of the semiconductor memory device increases. As a result, a size of the pipe latch circuit may hinder in designing a layout construction for internal circuits of the semiconductor memory device. Furthermore, a dimensional increase of the pipe latch circuit causes an increase of the overall chip size.